It is known that although the early failure occurrence rate of semiconductor integrated circuits is high, the failure occurrence rate after the occurrence of such an early life failure decreases. Therefore, burn-in testing is performed by applying heat or electrical stress to semiconductor integrated circuits prior to shipment testing to cause such an early life failure thereto.
FIG. 7 is a perspective view of a conventional burn-in board 2. Equally spaced on a board 4 of the burn-in board are a plurality of semiconductor integrated circuit sockets 5 and resistors 6, each of the semiconductor integrated circuit sockets 5 being secured with a plurality of screws 7 on the board 4 of the burn-in board. Formed in the semiconductor integrated circuit socket 5 is a contact electrode 9 which is made of elastic conductive materials and corresponds to a lead 8 of an elemental semiconductor integrated circuit 1. In addition, a guide post 10 is mounted for locating the lead 8 of the elemental semiconductor integrated circuit 1 in relation to the contact electrode 9. Further, a cover 11 is pivotally fixed to one end of the semiconductor integrated circuit socket 5.
When the cover 11 is securely closed on the semiconductor integrated circuit socket 5 provided with the elemental semiconductor integrated circuit 1, the cover 11 will press the lead 8, being placed on the contact electrode 9 in a contacting manner therewith, of the elemental semiconductor integrated circuit 1 against the elasticity of the contact a electrode 9, so that contact pressure can be obtained. A projecting lead pressuring section 12 is provided on the inside face of the cover 11 to press the lead 8 of the elemental semiconductor integrated circuit 1. Further, the cover 11 has a locking lever 13. The locking lever 13 is a lock lever which is disposed for keeping the cover 11 securely closed. Mounted in a location on the integrated circuit socket 5 corresponding to that of the locking lever 13 is a locking portion 14.
In the semiconductor integrated circuit sockets 5 and the covers 11, package escape openings 16 are formed in the corresponding locations to package sections 15 made of resin and ceramic of the elemental semiconductor integrated circuit 1. The semiconductor integated circuit socket 5 and the guide post 10 are integrally formed and mounted. Also, the cover 11 and the lead pressuring section 12 are integrally formed and mounted. All of these components are made from the same materials having electrical insulating characteristics.
A connector terminal 18 is formed at one end of the burn-in board 2. Via the connector terminal 18, a burn-in apparatus 3 to be described later is connected to the burn-in board 2. The connector terminal 18 and the contact electrode 9 are connected, via a plurality of fuses 17 and resistors 6, with each other by a pattern electrode (not shown).
Next, the elemental semiconductor integrated circuit 1 is placed on the semiconductor integrated circuit socket 5 in such a way that the lead 8 of the elemental semiconductor integrated circuit 1 fits to the contact electrode 9. At this time, the alignment of the lead 8 of the elemental semiconductor integrated circuit 1 with the contact electrode 9 is automatically made by means of the guide post 10 on the semiconductor integrated circuit socket 5. Because the package escape opening 16 is provided in the semiconductor integrated circuit socket 5, the package section 15 enters the package escape opening 16 so that the lead 8 will come into contact with the contact electrode 9.
Further, the cover 11, having the lead pressing section 12 corresponding to the lead 8 of the elemental semiconductor integrated circuit 1, is closed in the direction of the arrow B. At this time, the locking lever 13 of the cover 11 and the corresponding locking portion 14 of the semiconductor integrated circuit socket 5 are engaged with each other so that the cover 11 is kept securely closed. Also, provided in the cover 11 is another package escape opening 16. As the contact electrode 9 has elasticity, the lead 8 of the elemental semiconductor integrated circuit 1 is pressed by the cover 11 so that a reliable contact is established.
FIG. 8 is a perspective view of a conventional burn-in apparatus 3. A plurality of burn-in board racks 19 are equally spaced within the burn-apparatus 3. The burn-in boards 2 each carrying a plurality of the semiconductor integrated circuits 1 are accommodated in order in the burn of board racks 19 in the burn-in apparatus 3. The burn-in board 2 has the connector terminal 18. Each card edge type connector (not shown) is mounted in the respective inner parts of the burn-in board racks 19 for establishing circuit connections with the connector terminal 18, the number of which is equal to the number of the burn-in boards 2. Accordingly, the circuitry connection between the burn-in board 2 and the burn-in apparatus 3 will be automatically established when the burn-in board 2 is accommodated in the burn-in board rack 19. As a result, the circuit connection between the semiconductor integrated circuits 1 and the burn-in apparatus 3 is made. After burn-in testing is completed, the semiconductor integrated circuits 1 are taken out from the burn-in apparatus 3 in the reverse order of the accommodation step and then are forwarded to the next process of shipment testing.
FIG. 9 is a view showing one example of electrical signals to be input to the lead 8 of the semiconductor integrated circuit 1 during burn-in testing. Either a power supply potential Vcc, a ground potential GND or a synchronization signal CLK is input via the resistor 6 to the lead 8 which functions as an input terminal or a power supply terminal. This is because the input signals are controlled by the resistor 6 to a required level corresponding to the lead 8 so as to allow a variety of the semiconductor integrated circuits 1 to be tested by burn-in testing which employs only a single burn-in apparatus 3. Consequently, as many of the resistors 6 the leads 8 functioning as an input terminal are required. This has resulted in a defect that the area occupied by the resistors 6 becomes greater. Accordingly, the packaging density of the semiconductor integrated circuits 1 decreases.
With the semiconductor integrated circuits 1, they are different not only in size and in external circuit configuration but also in location of input/output terminals and power supply terminals depending on their type. Therefore, it is necessary to prepare the semiconductor integrated circuit socket 5 for each of the semiconductor integrated circuits 1. In addition, it is required that the burn-in board 2 suitable for the semiconductor integrated circuit socket 5 must be produced, which will lead to complicated problems such as the number of components for the semiconductor integrated circuit socket 5 and the burn-in board 2 increases. This drawback is one of the main factors leading to high costs in mass production processes.
In addition to the above problems, it is necessary that the mounting of the semiconductor integrated circuit 1 on the semiconductor integrated circuit socket 5 and the locking of the cover 11 are carried out for every semiconductor integrated circuit. Therefore, after burn-in testing is completed, the cover 11 must be opened for the installation and removal operations of the individual semiconductor integrated circuits 1. Accordingly, the mounting and removal operations of the semiconductor integrated circuit 1 to the burn-in board 2 become complicated. This causes another problem such as the installation and removal operations require a much longer amount of time.
FIG. 10 is a plan view illustrating the semiconductor integrated circuit 1 having semiconductor integrated circuit supporting sections 21 under production. The semiconductor integrated circuit 1, which includes the package section 15 and the leads 8, is connected to a lead frame 20 via lead tips 22 as shown with hatching. The semiconductor integrated circuit 1 is also connected to the lead frame 20 through the semiconductor integrated circuit supporting section 21. Tie-bars 23, as shown with hatching, are provided between the individual leads 8 and each of the leads 8 is connected with one another by the tie-bars 23.
FIG. 11 is a flow chart showing the manufacturing process of the semiconductor integrated circuit 1. The process a1 is a die bonding step of fixing semiconductor integrated circuit chips to the lead frame 20. Next, the process a2 is a wire bonding step wherein the integrated circuit chips are connected to the leads 8. The process a3 is a package sealing step which performs a sealing by using the package section made of resin or ceramic.
In the process a4, each semiconductor integrated circuit 1 is cut away from the lead frame 20 by cutting the lead tip 22, the tie-bar 23 and the semiconductor integrated circuit supporting section 21. Further, in the process a5, the lead 8 of the semiconductor integrated circuit 1 is to be bent. The process a6 is to "burn-in" the semiconductor integrated circuit 1 with the burn-in board 2 and the burn-in apparatus 3. In the final process a7, after burn-in testing is completed another testing is given to the semiconductor integrated circuit 1.
Alternatively, in the process a4, it is possible to cut only the lead tip 22 and the tie-bar 23 without cutting the semiconductor integrated circuit 1 from the lead frame 20 to leave the semiconductor integrated circuit 1 in a connecting relation to the lead frame 20 through the semiconductor integrated circuit supporting section 21. Where the semiconductor integrated circuit 1 is left in a connecting relation to the lead frame 20, there is no need of the installing and removing operations of the individual semiconductor integrated circuit 1 to the semiconductor integrated circuit socket 5 so that such installation and removal operations may be easily carried out. However, neither the integrated socket 5 nor the burn-in board 2 capable of "burning-in" the semiconductor integrated circuit 1, which is still in a connecting relation to the lead frame 20, is now available. Accordingly, the step of burn-in testing is forced to be skipped, or it is necessary to employ another burn-in method for individually installing and removing the semiconductor integrated circuit 1 by means of the burn-in board 2. In the event that burn-in testing on the semiconductor integrated circuit 1 is skipped, it is possible that the failure occurrence rate of the semiconductor integrated circuits 1 may increase after shipment. As a result, the problem that the reliability of the semiconductor integrated circuits 1 declines will arise.